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EAGLE Library Object

File details

File name:m-pad-2.1.lbr
Uploaded by:Juergen Messerer
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Object details

Name:DS90C363B_DS90C365_THC63LVDM63R
Type:device
Description:National Smeiconductors DS90CF363B +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz

General Description:

The DS90CF363B transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18
bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbytes/sec. The DS90CF363B is
fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF366) without
any translation logic.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

Features: No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered. Support Spread Spectrum Clocking up to 100KHz frequency modulation & deviations of ±2.5% center spread or 5% down spread. "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high. 18 to 68 MHz shift clock support Best-in-Class Set & Hold Times on TxINPUTs Tx power consumption < 130 mW (typ) @65MHz Grayscale 40% Less Power Dissipation than BiCMOS Alternatives Tx Power-down mode < 37?W (typ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. Narrow bus reduces cable size and cost Up to 1.3 Gbps throughput Up to 170 Megabytes/sec bandwidth 345 mV (typ) swing LVDS devices for low EMI PLL requires no external components Compatible with TIA/EIA-644 LVDS standard Low profile 48-lead TSSOP package Improved replacement for: SN75LVDS84, DS90CF363A
National Smeiconductors DS90C365 +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-85 MHz

General Description:

The DS90C385 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85
MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at
a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec. Also available
is the DS90C365 that converts 21 bits of LVCMOS/ LVTTL data into three LVDS (Low Voltage Differential Signaling)
data streams. Both transmitters can be programmed for Rising edge strobe or Falling edge strobe through a
dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver
(DS90CF366) without any translation logic. The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch
ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

Features: 20 to 85 MHz shift clock support Best?in?Class Set & Hold Times on TxINPUTs Tx power consumption

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DS90C363B_DS90C365_THC63LVDM63R

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