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EAGLE Library Object
|Uploaded by:||Juergen Messerer|
|Remarks:||This library is a part of the archive file m-pad-2.1.zip|
Show other files in the archive
|Download options:||Download whole archive|
( 303.9 KiB )Download original file
( 1,153.0 KiB )Download file converted
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( 2,969.6 KiB )
|Description:||Quick Logic's QuickIDE Intel XScale PXA2xx to IDE Bridge|
The QuickIDE device is a full featured IDE Controller companion device for the Intel XScale PXA2xxx line of
embedded processors. This device offers extremely high throughput while consuming very little power. With its
on-board Sector Buffer RAM, the device allows the XScale CPU to perform read and write operations in full 512-
byte sectors without interruption or waiting for the externally connected IDE device to be 'ready'.
This device connects to the XScale CPU via its static memory interface. Variable Latency Input and Output
(VLIO) is handled automatically by the QuickIDE device through use of the RDY signal. The RDY signal is only
used to properly synchronize the QuickIDE device's responses to the XScale read and write commands during
high-speed bus operation the QuickIDE device does not assert the RDY signal while it is waiting for responses
from the externally connected IDE device. Instead, after an IDE command is given to the QuickIDE device, an
interrupt is asserted to the XScale CPU to indicate that the externally connected device has responded and that
the internal sector buffer is ready for read or write.
Although the IDE interface is 16-bits wide, the QuickIDE device 'stacks' the IDE data words properly in the
internal sector buffers so that the XScale device can perform all read and write operations in 32-bit mode.
The QuickIDE device is based upon QuickLogic's proven programmable logic ViaLink® technology and is
implemented in the QL8050 device in a 196-pin plastic (0.8 mm ball pitch) BGA package.
Features: IDE Controller
- PIO Mode 0 to PIO Mode 4 Support with MultiWord DMA
- Internal IDE Sector Buffering for Increased Performance (Back-to-Back ?Prefetch? Sector Transfers)
- Controller Performance Close to Maximum PIO Mode Performance
- In Prefetch MWDMA Mode, 32-bit XScale Transfers Using Flow-Through DMA
- PIO4 Mode Supports 15.25 MBytes/sec (Excluding OS Overhead)
- Greter than 10MBytes/sec Transfers Measured Under WinCE 5.0
- Internal ATA Timing Registers for PIO Modes
- Compact Flash/PCMCIA Card Compatible in TRUE-IDE/ATA Mode
Glueless Connection to Intel XScale Static Memory Interface
- Uses One Chip Select and Eleven Address Lines
- RDY Signal Implemented for Variable Latency Support (VLIO)
- 32-bit XScale Transfers Supported
- Compatible with XScale Flow-Through DMA Transfers
Selectable Low Power Mode
- Controlled by Discrete Input Pin
- Reduces Overall Power Consumption to Less than 1mW
Can Power Up/Down to Connected IDE Device Via External Switch
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